1. Field of the Invention
The present invention relates to a voltage level clamping circuit and a comparator module, and more particularly, to a voltage level clamping circuit which can be implemented in an integrated circuit (IC) and a high-speed comparator module.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 shows a simplified block diagram of a conventional driver integrated circuit (IC) 100 and a circuit board 110 of a LCD panel (not shown) in accordance with a prior art, wherein a voltage level of a P-type substrate 120 of the driver IC 100 is in a normal operation period. As shown in FIG. 1, in the driver IC 100, since the driver IC 100 is designed for high voltage operation, using a negative bias voltage (such as −16V) for the P-type substrate 120 is a common way to ensure that the driver IC 100 operates normally. The required negative bias voltage for the P-type substrate 120 is attained by using a charge pump 130, however, when the driver IC 100 has just started up, the required negative bias voltage for the P-type substrate 120 is not yet formed, and if an external voltage source VGL has a positive voltage at this time, the positive voltage will forward bias a parasitic diode 124 between the P-type substrate 120 and an N well 122, so as to generate a latchup effect and damage the driver IC 100. Please refer to FIG. 2. FIG. 2 shows another simplified block diagram of the conventional driver IC 100 and the circuit board 110 in accordance with the prior art, wherein the voltage level of the P-type substrate 120 of the driver IC 100 is in a start-up operation period.
Please refer to FIG. 3. FIG. 3 shows yet another simplified block diagram of the conventional driver IC 100 and the circuit board 110 in accordance with the prior art, wherein the prior art adds a Schottky diode 140 outside the driver IC 100 to solve the above problem. In this way, when the voltage level of the external voltage source VGL is greater than 0.3V (i.e., when a ground voltage source AGND is lower than the external voltage source VGL), the Schottky diode 140 will conducted and then the voltage level of the external voltage source VGL will be clamped, so as to prevent the latchup problem generated by forward biasing the parasitic diode 124 between the P-type substrate 120 and N well 122 in the driver IC 100. There will be a high product cost problem with this kind of conventional circuit scheme, however, since it requires additional external elements to be implemented.